1. Field of the Invention
The present invention relates to a clamping circuit for video signal and more particularly, to a clamping circuit for dc-clamping once an analogue video signal of a positive polarity synchronization type in which frame synchronizing signal exists in the range of the level of a video signal, such as a high-resolution television signal whose bandwidth is compressed by a multiple sub-nyquist sampling system before analogue-to-digital conversion in order to detect the frame synchronizing signal from the digital signal to which the analogue video signal is converted.
2. Description of the Prior Art
A high-resolution television signal proposed by Japan Broadcasting Corporation (NHK) is an analogue video signal of a positive polarity synchronization type as described above, which is discussed in, for example, "Nikkei Electronics", Mar. 12, 1984, pp. 112-116. More specifically, the high-resolution television signal has a horizontal synchronizing signal H having an inclined portion and a frame synchronizing signal F comprising 17.5 times repetitive pulses. The horizontal synchronizing signal H is inserted into each line, and the frame synchronizing signal F is inserted into the 605th line and the 606th line with polarities opposite to each other.
FIG. 2 shows main portions of a high-resolution television receiver for receiving such a high-resolution television signal and reproducing a high-resolution video signal. The high-resolution video signal (referred to as video signal hereinafter) is inputted to an input terminal 1. A clamping circuit 2 is responsive to a clamping pulse as described below for dc-clamping the video signal inputted to the input terminal 1. A low-pass filter 3 cuts an unnecessary high frequency component of the video signal outputted from the clamping circuit 2. An A/D converter 4 converts the output signal from the low-pass filter 3 into a digital signal in 8-bit parallel representing 256 tone wedges. A digital processing portion 5 performs interframe interpolation, interfield interpolation, TCI decoding and the like of the digital signal outputted from the A/D converter 4 and restores the digital signal to a base band video signal. A D/A converter portion 6 restores the output signal of the digital processing portion 5 to an analogue video signal and applies the same to a television picture tube 7.
On the other hand, the most significant digit of the output signal of the A/D converter 4 is applied to a frame synchronizing signal detecting circuit 8. The frame synchronizing signal detecting circuit 8 detects the frame synchronizing signal F based on the most significant digit of the output signal thereof and generates a horizontal synchronizing pulse HP and a vertical synchronizing pulse VP by utilizing as a reference the frame synchronizing signal F. A clamping pulse generating circuit 9 generates a predetermined clamping pulse CP at predetermined timing as described below within a vertical blanking time period in the analogue video signal inputted to the input terminal 1 based on the horizontal synchronizing pulse HP and the vertical synchronizing pulse VP from the frame synchronizing signal detecting circuit 8.
Detailed description is now made on an operation for detecting the frame synchronizing signal F by the frame synchronizing signal detecting circuit 8. A low level and a high level of the frame synchronizing signal F (in FIG. 1) are selected at levels of 25% (64/255) and 75% (192/255) of the amplitude of the video signal, respectively. Consequently, if the frame synchronizing signal F is converted from an analogue signal to a digital signal, the low level and the high level thereof become 01000000 and 11000000, respectively. Thus, when the frame synchronizing signal F is correctly outputted from the A/D converter 4, the most significant bit of the output signal of the A/D converter 4 comprises the defined number of regular repetitions of "0" and "1", which is utilized for detecting the frame synchronizing signal F.
On the other hand, the clamping circuit 2 performs the following operation as preliminary processing for detecting such a frame synchronizing signal. More specifically, a signal at a level corresponding to 50% of the amplitude of the video signal is inserted into the 5-th line or the 567-th line within a vertical blanking time period in the video signal as a reference level for clamping. The clamping circuit 2 is responsive to the above described clamping pulse CP for clamping the reference level of the video signal at a clamp potential V.sub.0. The clamp potential V.sub.0 is set in the middle value of a range R of input voltage of A/D converter 4.
Thus, if and when the above described reference level (50%) is correctly clamped at the clamp potential V.sub.0 as shown in FIG. 3(a), the frame synchronizing signal F is correctly located in 25 to 75% of the above described range R of input voltage, so that the high level and the low level thereof are converted into the above described digital values 01000000 and 11000000 in the A/D converter 4. As a result, the frame synchronizing signal F is detected in the above described manner. When not the reference level itself but a level (level in the range of the amplitude of the frame synchronizing signal F, that is, 25 to 75% of the range R of input voltage) in the vicinity of the reference level is clamped at the clamp potential V.sub.0 in the unstable state, for example, immediately after reception is started, the frame synchronizing signal F is not converted into the above described normal digital value. However, since the most significant digit of the frame synchronizing signal F comprises repetition of "1" and "0" as at the time of the normal operation, the frame synchronizing signal F can be also detected in this case.
However, in the above described unstable state, for example, immediately after reception is started, it is assumed that a video signal, by which level the entire picture becomes black or white, for example, continues for several fields before the frame synchronizing signal F is detected. In such a state, since the clamping pulse CP from the clamping pulse generating circuit 9 is not in a normal timing position, a black level or a white level of the video signal is clamped at the above described predetermined clamp potential V.sub.0 by the clamping pulse CP. FIGS. 3(b) shows the case in which the black level (0%) is clamped at the clamp potential V.sub.0. In this case, since the frame synchronizing signal F is located in 75 to 100% of the range R of input voltage, the most significant digit of the digitalized frame synchronizing signal F is always "1". Portions represented by the broken line in FIGS. 3(b) are cut by a limiter operation in the A/D converter. Thus, the frame synchronizing signal F cannot be detected.